Traditionally, digital information storage stored information by toggling each cell between two states; a neutral state and a charged state in what is called a single-level cell (“SLC”) design. In non-volatile memory storage systems used today, it is a common practice to have memory chips capable of storing more than one bit per cell. Multi-Level Cell (“MLC”) devices, for example, store more than one bit per cell, where each bit is associated with or belongs to another page.
In an MLC flash that is capable of storing two bits per cell, each cell has a neutral voltage and three levels of charged states, for a total of four different states capable of storing two bits of information. Each state is actually a voltage range and not a single voltage level. The cell's “state” is represented by the cell's threshold value that is required to allow conduction of current. Therefore, such an MLC cell supports four different valid ranges that correspond to four different states. An MLC flash that supports more than two bits per cell will have more than four possible states.
In such memory storage systems, data is typically programmed to multiple pages simultaneously. In other words, a group of pages may be programmed in parallel.
However, such implementation may result in the shortcoming that if only part of the group of pages of the flash memory are being programmed, the controller may have to wait until programming is finished to be able to start the programming of the rest of the pages of this group. Since the data could have been programmed to the entire group of pages at the same time, this results in performance degradation. This is particularly so during the substantially long upper data page programming, as described herein below with respect to FIGS. 1A and 1B.
FIGS. 1A and 1B (prior art) show threshold voltage distribution for a typical memory cell of an MLC memory device. Programming of an MLC memory device storing two bits per cell is applied in two steps—in the first step, a lower data page is programmed, and in the second step, an upper data page is programmed. An exemplary threshold voltage distribution associated with the programming of a lower data page is shown in FIG. 1A. An exemplary threshold voltage distribution associated with the programming of an upper data page is shown in FIG. 1B.
FIG. 1A (prior art) shows the threshold voltage distribution for programming a lower data page. FIG. 1A has two voltage distributions, each distribution corresponding to one state. The different distributions of the threshold voltage are used for encoding the values of the bits stored in the cell. The “X-axis” represents threshold value in Volts. The “Y-axis” represents number of cells in a memory array. Curve Er in FIG. 1A represents a distribution of the threshold values of the cells within the memory array that is in the erased data state Er, and curve A represents a distribution of the threshold values of the cells within the memory array that are in data state A.
In FIG. 1A, the graph's voltage distribution are labeled (from left to right) “1” and “0”. This means that when a cell is in the erased data state Er (the first state from the left), it represents a “1” for the bit stored in this cell, and when the cell is in data state A, it represents a “0” for the bit stored in this cell. Note that encoding of states as presented herein is arbitrary, and other encoding schemes may hold.
FIG. 1B (prior art) shows the threshold voltage distribution for programming an upper data page of an MLC memory device. FIG. 1B has four voltage distributions, each distribution corresponding to one state. The different distributions of the threshold voltage are used for encoding the values of the bits stored in the cell. The “X-axis” represents threshold value in Volts. The “Y-axis” represents number of cells in a memory array of an MLC memory device. Curve Er in FIG. 1B represents a distribution of the threshold values of the cells within the memory array that is in the erased data state Er. In the same manner, curves A, B, C represent a distribution of the threshold values of the cells within the memory array that are in data states A, B, C, respectively.
In FIG. 1B, the graph's voltage distributions are labeled (from left to right) “11”, “10”, “00”, “01”, where the first binary digit represents the value stored in the lower data page, and the second binary digit represents the value stored in the upper data page. This means that when a cell is in the erased data state Er (the first state from the left), it represents a “1” for the lower bit and a “1” for the upper bit. When a cell is in state A, it represents a “1” for the lower bit and a “0” for the upper bit. When a cell is in state B, it represents a “0” for the lower bit and a “0” for the upper bit. When a cell is in state C, it represents a “0” for the lower bit and a “1” for the upper bit. Note that encoding of states presented herein is arbitrary, and other encoding schemes may hold.
Due to the distribution of the memory cells, average read and write times of an upper data page are longer than of a lower data page, resulting in worse performance. This is so since the difference between the threshold voltage ranges assigned to an upper data page is much smaller than in a lower data page (i.e., there is much less margin between the four data states of a two-bit cell than between the two data states of a single level cell). In other words, while using an MLC flash for storing more than one bit per cell allows more data storage per transistor—and is hence cheaper—reading more finely differentiated voltage ranges requires finer measurement, which is in turn slower and more error-prone.
A disturbance in the threshold value (i.e., leakage of stored charge causing a threshold voltage drift or interference from operating neighboring cells) that is insignificant in a lower data page because of the large gap between the two states, may cause erroneous programming of data onto an upper data page. This requires programming of an upper data page with an increased degree of precision, which typically takes longer time.
Therefore, if only part of a group of upper data pages of a flash memory is programmed, the controller may have to wait until the long programming finishes before the controller can commence programming the rest of the upper data pages in this group.
There is therefore a need to address programming of data associated with non-volatile memories in a way that would increase overall system performance.